Design Engineer V/ASIC Power Engineer
Job Description
Job Title: Design Engineer V – ASIC Power Engineer
Location: Sunnyvale, CA (Hybrid)
Duration: 6 Months (Potential extension up to 2 years)
Job Summary:
We are seeking an experienced ASIC Power Engineer to support power analysis and optimization for advanced AR/VR chip development programs. This role focuses on PPA optimization, RTL/netlist-level power analysis, and low-power design methodologies using industry-standard EDA tools.
Key Responsibilities:
- Perform PPA optimization using Fusion Compiler
- Conduct RTL & netlist-level power analysis
- Analyze ASIC flow reports (Synthesis, PD, Power, Timing)
- Develop scripts for data extraction & analysis (Python/Tcl/Perl)
- Implement RTL blocks and UPF-based power intent
- Support power optimization across IP/SoC designs
Required Skills:
- 10+ years of experience in ASIC power optimization
- Strong experience with Synopsys (DC, ICC, PrimePower/PTPX, VCS, Verdi) or Cadence Joules
- Expertise in low-power design methodologies & UPF
- Strong scripting skills (Python, Perl, Tcl)
- Experience with Silicon power characterization
Preferred Skills:
- Power profiling at IP/SoC level
- Data analytics & visualization experience
- MATLAB / Excel modeling experience
Education:
BS in Electrical Engineering, Computer Science, or equivalent experience